Careers

Location: Tempe, AZ

Description::

Design schematics and layout ATE Printed Circuit boards using Cadence Allegro design tools.

Generate final documentation for manufacturing which will include Gerber Files, Fabrication drawings, Assembly drawings and other design files.

Work with customers to make sure PCB layout meets PCB design requirements.

Perform all the PCB layout design activities including schematic review, part library creation, component placement, trace routing, and Gerber generation. Create, modify, and maintain Allegro part libraries based on component datasheets and drawings.

Set up and maintain Design Rule Check (DRC) based on DFM/DFT rules using Constraint Manager.

Qualifications:

Qualified candidates should have at least 1-2 years of experience and possess knowledge of Cadence Allegro v16.3
An Associate’s Degree in Electronics or equivalent experience is preferred.

Email Resume to:

[email protected]

Mail Resume to:

1145 W. Fairmont Dr.
Tempe, AZ 85282